Artificial Intelligence | News | Insights | AiThority
[bsfp-cryptocurrency style=”widget-18″ align=”marquee” columns=”6″ coins=”selected” coins-count=”6″ coins-selected=”BTC,ETH,XRP,LTC,EOS,ADA,XLM,NEO,LTC,EOS,XEM,DASH,USDT,BNB,QTUM,XVG,ONT,ZEC,STEEM” currency=”USD” title=”Cryptocurrency Widget” show_title=”0″ icon=”” scheme=”light” bs-show-desktop=”1″ bs-show-tablet=”1″ bs-show-phone=”1″ custom-css-class=”” custom-id=”” css=”.vc_custom_1523079266073{margin-bottom: 0px !important;padding-top: 0px !important;padding-bottom: 0px !important;}”]

SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension

The New API Adds Critical Capabilities to Widely Used Compilers, GCC & LLVM

SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, announced several new updates to their leading RISC-V portfolio in the areas of security, and vector processing. In collaboration with the Barcelona Supercomputing Center, SiFive created an API for vector intrinsics for popular open-source compilers GCC, and LLVM. Additionally, SiFive reports that the SiFive Shield Hardware Cryptographic Accelerator (HCA) true random number generator (TRNG) has successfully passed conformance evaluation to SP 800-90B standard, to enable FIPS 140 certified security solutions.

Recommended AI News: Litmus and Oden Partner to Offer Complete IIoT Solution for Smart Manufacturing

RISC-V Vector Processing

The new API will speed up the development of vector processor applications using RISC-V processor cores with RISC-V Vector Extension (RVV) 1.0 support, such as the upcoming SiFive Intelligence line of products. The API is available on Github now and will be upstreamed to GCC and LLVM compilers once the RVV specification is ratified. SiFive’s previously added upstream support for the RISC-V ISA to GCC in 2017, and expects to continue to work with the RISC-V community to ensure the API is aligned to the final RVV 1.0 specification. Learn more about SiFive’s open-source contributions for RISC-V Vectors in our blog, here.

Related Posts
1 of 30,395

“The RISC-V Vector extension will enable new RISC-V based processor designs to accelerate many workloads, from AI to signal processing and scientific research,” said Chris Lattner, President of Platform Engineering, SiFive. “With the integration of support for intrinsics in popular compilers, the RISC-V community is enabled to create efficient, scalable hardware and software solutions to address modern computing challenges.”

Recommended AI News: Asian Edutech Platform Unacademy Raises $150 Million

SiFive Shield SoC-level Security

The SiFive’s Shield Hardware Cryptographic Accelerator (HCA) was introduced in the recent SiFive 20G1 release in July, enabling the acceleration of cryptographic functions used to securely boot an SoC, protect communications, and restrict access to the debug interface. The SiFive HCA IP block includes a 100% digital true random number generator (TRNG) that has successfully passed a conformance evaluation against the stringent NIST SP-800-90B recommendation for entropy sources used for random bit generation. Learn more about SiFive Shield HCA in our blog, here.

SiFive will release more updates to its RISC-V-based Core IP portfolio in October, with enhanced performance for the SiFive 7-Series range of U-, S-, and E-Series processor cores. These updates will improve performance in Artificial Intelligence workloads where data streaming performance is important, and be deployed to all customers using the award-winning SiFive’s Core Designer automatically.

Recommended AI News: Developer-Centric Application Security Company StackHawk Announces Its General Availability Launch

1 Comment
  1. Joanna says

    Hello. Ԍreat job. I did not anticipate this.
    This is а impressive story. Ꭲhanks!

    My ԝeb Ьlog seo expert (Joanna)

Comments are closed, but trackbacks and pingbacks are open.