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EdgeCortix Acquires Multiple Patents for Dynamic Neural Accelerator AI Processor Technology

EdgeCortix Inc., the company that enables efficient AI processing at the edge with near cloud-level performance, announced that it has been granted four patents on their artificial intelligence specific, runtime reconfigurable processor technology.

“The four patents acquired in Japan and USA are fundamental technologies behind our Dynamic Neural Accelerator (DNA) hardware architecture, a highly energy-efficient and low-latency AI accelerator IP, designed specifically for on-device machine learning. DNA in combination with a proprietary software stack is the technology behind EdgeCortix’s first co-processor chip for AI inference. These patents further strengthen the differentiation of our DNA technology against its competitors and are important additions to our existing portfolio of patents across hardware processor and compiler technologies,” commented Sakyasingha Dasgupta, CEO of EdgeCortix group companies and one of the inventors of the acquired patents.

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JP Patent No6834097
Patent Issue Date: 
8th February 2021
Title of Invention: Neural Network Accelerator Hardware Specific Division of Inference

US Patent App. No. 17/186,003 (granted)
Date of Notification: 18th August 2021
Title of Invention: Neural Network Accelerator Hardware Specific Division of Inference into Groups of Layers

Assignee: EdgeCortix Pte. Ltd.

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Invention Summary: This invention covers the generation of instructions to perform inference by a hardware system, such as an ASIC or an FPGA, capable of performing efficient neural network inference by grouping neural network layers and avoiding external memory accesses between processing them to reduce the total number of external memory accesses as compared to processing the layers one by one and storing all intermediate data in an external memory. This may allow flexibility in handling various neural networks with performance and power efficiency close to a fixed-neural-network chip, and flexibility to handle a variety of neural networks, such as convolutional neural networks, including MobileNet variations. Such techniques may be beneficial in conditions when an entire input layer cannot fit into limited on-chip memory. By reducing external memory accesses, stochasticity in performance may be reduced as well.

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US Patent No. 11144822
Patent Issue Date: 
12th October 2021
Title of Invention: Neural Network Accelerator Run-time Reconfigurability

JP Patent App. No. 2021-079197 (granted)
Date of Notification: 8th September 2021
Title of Invention: Neural Network Accelerator Run-time Reconfigurability
Assignee: EdgeCortix Pte. Ltd.

Invention Summary: This invention covers devices for performing neural network inference, such as an accelerator, that include a novel “reduction interconnect”, between its compute modules and its on-chip memory for accumulating compute module outputs on-the-fly, avoiding the extra read from and write to on-chip memory.  The reduction interconnect is reconfigurable to establish connections between the compute modules, bypassing on-chip memory, in a manner that results in efficient run-time inference of entire tasks or portions of such tasks.  For example, in an accelerator for inference of any deep neural network, the reduction interconnect may allow, for every compute module, selecting between direct access to memory or access through an auxiliary adder circuit.  The freedom to select the connectivity may allow an accelerator to compute multiple input channel tiles or kernel pixels in parallel, with multiple compute modules working fully synchronously.

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