Si2 Forum Addresses Novel Approaches to Low-Power Semiconductor Design

Strategies for low-power and energy-efficient semiconductor design and how standards can advance these critical technologies is the focus of a Silicon Integration Initiative forum scheduled during the upcoming Design Automation Conference in San Francisco.

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“Advanced system design architectures are limited by efficiency and scalability of low-power analysis”

Power and Energy Efficiency in the Age of AI will be held Monday, July 11, 11:30 a.m. – 3:30 p.m., in Room 215 of the AMA Conference Center, located in the San Francisco Marriott Marquis. Admission is free and space is limited. Attendance via webinar is also available.

Cosponsored by IEEE CEDA, the Si2 Low-Power Forum features ten leading semiconductor design architects, academics, and practitioners of electronic design automation. They will present novel strategies and solutions for speeding the adoption of low-power design, and fabrication of semiconductors.

Forum Agenda

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“Advanced system design architectures are limited by efficiency and scalability of low-power analysis,” said Leigh Anne Clevenger, Si2 vice president, technology. “Experts from industry and academia will present challenges and strategies that push the envelope on low-power and energy-efficient design. This foundation can lead to a roadmap of low-power to thermal management for such emerging vertical markets as autonomous, 5G to 6G transition, edge-compute and AI/ML.”

Si2 is also hosting a workshop on potential enhancements to the P2416 standard, including its own contributions and plans to meet design and research goals for low-power analysis. IEEE P2416 Power Modeling for System-Level Analysis is scheduled for Tuesday, July 12, 1:30 p.m. – 3:00 p.m. in Room 215 of the AMA Conference Center.

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