Cadence Delivers 13 New VIP and Expands System VIP Portfolio to Accelerate Automotive, Hyperscale Data Center and Mobile SoC Verification

Cadence Design Systems, announced the availability of 13 new Verification IP (VIP) solutions that enable engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols. The new Cadence VIP offerings empower customers to confidently develop their next-generation automotive, hyperscale data center and mobile SoCs and microcontrollers while keeping pace with the latest industry standards, including Arm AMBA 5 CHI-f, Universal Chiplet Interconnect Express (UCIe), GDDR7, DDR5 DIMM, MIPI A-PHY and SoundWire I3S, and USB4 2.0 interfaces.

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“The Cadence memory VIP is a critical part of our verification process and instrumental in the successful deployment of our memory PHY IP”

The new Cadence VIP offer customers a comprehensive verification solution for the most complex protocols. Cadence customers have access to a consistent application programming interface (API) across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption. The VIP support multiple application areas and specifications, including:

• Hyperscale data center:
  • UCIe
  • AMBA 5 CHI-f
  • DTI
  • Latest version of DDR5 DIMM
• Automotive:
  • MIPI A-PHY 1.1
  • CAN XL
  • Flash ONFI 5.1
• Consumer and mobile:
  • USB4 2.0
  • GDDR7
  • MIPI SoundWire I3S (SWI3S)
  • Latest version of LPDDR
  • DFI
  • HDMI 2.1

All Cadence VIP solutions include Cadence TripleCheck^™ technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The new VIP also support the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers. Using the expanded System VIP portfolio, customers can experience up to 10X efficiency improvements compared to a manual process for SoC verification.

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“The Cadence memory VIP is a critical part of our verification process and instrumental in the successful deployment of our memory PHY IP,” said Ricky Lau, co-founder and CTO of The Six Semiconductor Inc. “Cadence continues to deliver new VIP offerings and advanced SoC verification technologies that support the latest standards. The Cadence VIP offerings have significantly reduced our development time and increased the confidence of our customers.”

“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “With these 13 new VIP, Cadence is offering customers solutions to ensure the designs comply with the standard specifications as well as application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”

The new VIP solutions are part of the broader Cadence verification full flow, which includes Palladium^® Z2 emulation, Protium^™ X2 prototyping, Xcelium^™ simulation, the Jasper^™ Formal Verification Platform, the Helium^™ Virtual and Hybrid Studio, and the Verisium^™ AI-Driven Verification Platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day. The VIP solutions and verification full flow support the company’s Intelligent System Design^™ strategy, enabling SoC design excellence.

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