Signaloid Announces Preview of New ASIC Targeted at Physical AI and Robotics Applications

Signaloid , a computing platform company providing hardware and binary-translation-based acceleration of AI, robotics, aerospace, and quantitative finance workloads, announced the tapeout and preliminary specifications documents for its C0-ASIC. Delivery of engineering samples to the first customer is due in Q3 2026 and additional FPGA-based systems implementing the ASIC’s design are under discussion for deployment in the UK and Switzerland later in 2026.

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Signaloid’s distribution-extended compute hardware (UxHw) builds on new mathematical techniques to restructure computations, dynamically, to achieve the same results as conventional hardware while often using 1000-fold less energy.

The C0-ASIC was targeted specifically at energy-efficient physical AI workloads. The UK Advanced Research and Invention Agency (ARIA) will take delivery of systems based on the ASIC for use in next-generation AI workloads such as second order methods.

“The Scaling Compute program at ARIA commissioned several innovative technology prototypes pursuing unconventional ideas to design new AI accelerators,” says ARIA Program Director Suraj Bramhavar. “We commissioned Signaloid’s C0-ASIC for evaluation in randomized numerical linear algebra and probabilistic computing workloads. We believe randomized linear algebra represents a fundamentally new and powerful technique underpinning many applications in computer science including AI, and exploiting these principles in hardware could provide an entirely new vector for improved performance. We are excited to invest behind this theme, in partnership with Signaloid, to explore its full potential.”

A Different Kind of AI Compute Accelerator

The C0-ASIC implements Signaloid’s distribution-extended compute hardware (UxHw^®) technology.

Unlike conventional CPUs and GPUs, which use impressive amounts of sheer compute force across thousands of compute cores, to solve problems that require iterative randomized variations, Signaloid’s UxHw builds on new mathematical techniques to restructure computations, dynamically, to achieve the same results while often using 1000-fold (or more) less energy.

The UxHw technology and its implementation is covered by a growing portfolio of over 90 intellectual property filings in the US, China, Taiwan, Japan, and the EU.

An International Partnership

The design and implementation were the result of a collaboration between Signaloid and world-leading design partners IC-Link by imec and US-based Cadence Design Systems.

“Leading AI hardware innovators trust IC link as a key partner to bring their most advanced ASIC concepts through design and into production with our foundry partner TSMC,” says Ozgur Gursoy, Director Portfolio & Strategy for IC-Link’s ASIC services. “We are proud to have partnered with Signaloid in bringing the C0 Dreadnought ASIC from concept through the design cycle, enabling a new class of compute efficiency for distribution-enhanced computing applications.”

Speaking of the partnership, John Heighton, sales group director, EMEA North and Central at Cadence, said, “Cadence sets the industry standard for enabling leading companies to tape out cutting-edge AI silicon, including Signaloid’s C0-Dreadnought, now in production at TSMC. We support startups advancing next-generation computing by delivering our high-performance Artisan SRAM memories for Signaloid’s ASIC.”

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