Cadence Introduces Conformal Litmus to Deliver Fastest Path to Full-Chip Constraints and CDC Signoff

Next-Generation Constraints Signoff and CDC Signoff Solution Provides up to 10x Faster Turnaround Time and 100% Signoff Timer Accuracy

Cadence Design Systems, Inc. unveiled the Cadence Conformal Litmus, the next-generation solution that provides constraints signoff and clock domain crossing (CDC) signoff, reducing overall design cycle times and enhancing the quality of silicon in complex system-on-chip (SoC) designs. The Conformal Litmus provides designers with 100% signoff timer accuracy and up to 10X faster turnaround time versus the previous generation solution.

The @Cadence Conformal Litmus is a next-generation solution that provides constraints signoff and clock domain crossing CDC signoff, reducing overall design cycle times and enhancing the quality of silicon in complex SoC designs.

The new Conformal Litmus provides customers with the following:

• Industry’s first signoff static timer integration: With this integration, the Conformal Litmus can accurately model the design and the constraints using the same interpretation as the Tempus™ Timing Signoff Solution, providing customers with 100% signoff accuracy at the register-transfer level (RTL).
• CDC structural signoff: This verifies structural correctness of CDC in the design from early RTL through implementation flows. Smart analysis and reporting features provide rapid signoff capabilities, potentially saving weeks to months in the design schedule.
• Constraints signoff: Checks for correctness and completeness of constraints at the block level and lets users perform hierarchical block versus top consistency checks at the SoC integration level. The Conformal Litmus smart analysis generates accurate, low-noise reports that shorten debug time and helps users achieve signoff-quality constraints rapidly.
• Multi-CPU parallelization: Verification can be parallelized across multiple cores, delivering up to 10X faster turnaround time on SoC designs.

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“Accelerating SoC delivery to meet tight design schedules while keeping development costs down continues to be a growing customer challenge with today’s complex designs,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “The new Cadence Conformal Litmus provides innovative capabilities that enable our customers to sign off on constraints and CDCs and tape out reliable, high-quality designs on schedule.”

The Conformal Litmus is part of the broader Cadence digital and signoff full flow portfolio which provides better predictability and a faster path to design closure. It supports Cadence’s Intelligent System Design strategy, enabling SoC design excellence.

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Endorsements

“With the Cadence Conformal Litmus solution’s multi-CPU parallelization capabilities, we are able to complete runs on designs as large as 50M instances in under 10 hours. The solution provides us with the accuracy, speed and fast debug capabilities we need, and we expect to tape out with minimal iterations on quality of timing constraints between our design and implementation teams.”
– Hideyuki Okabe, director, Digital Design Technology Department, Shared R&D EDA Division, IoT and Infrastructure Business Unit, Renesas

“Our objective is to enable first-pass silicon success for customers with silicon-proven IP and robust design methodologies for ASIC designers facing increased design complexity, higher cost and shorter development cycles. The IP and ASICs we develop have extremely complex CDC structures, including handshake synchronizers, bus synchronizers and FIFOs. CDC signoff tends to be cumbersome, since often the engineer entrusted with CDC verification has no knowledge of the design intent. The Cadence Conformal Litmus, after performing comprehensive analysis, presents the results in a very intuitive way. All insights required to understand the CDC intent and also timing constraints checks at RTL are readily available. This helps us rapidly sign off and effectively saves significant time in the schedule.”
– Vikram Kuralla, director of engineering, Invecas

“We develop, create and license high-efficiency and high-quality semiconductor IP for automotive, industrial and other applications. We need to ensure that our IP is exhaustively verified and delivered ahead of time. CDC signoff is an important step in achieving this milestone. After evaluating the Cadence Conformal Litmus, we were impressed with its CDC capabilities, especially the smart analysis and reporting. This will enable us to quickly identify missing, invalid and incorrect CDC synchronization schemes in our designs. With the intuitive diagnosis capabilities, we expect that it will significantly accelerate our CDC signoff process.”
– Susumu Abe, general manager, Semiconductor IP & R&D Unit, Processor Development Department at NSITEXE, Inc.

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