Moortec announced the delivery of its In-Chip Monitoring solution on TSMC 7nm FinFET process to the new Arm® Neoverse™ N1 System Development Platform (SDP). As market leaders, Moortec supported integration and utilization of its process, voltage, and temperature (PVT) sensing subsystem technology to the platform, enabling the next-generation cloud-to-edge infrastructure, powered by Arm Neoverse solutions. The Neoverse N1 SDP is the industry’s first 7nm infrastructure-specific system development platform, enabling asymmetrical compute acceleration through the CCIX interconnect architecture. The collaboration between Moortec and Arm achieved a solution capable of dynamically sensing in-chip conditions to help optimize power consumption, maximize system speed, and enhance device reliability. The Neoverse N1 SDP is available to hardware and software developers for hardware prototyping, software development, system validation, and performance profiling/tuning.
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“Arm Neoverse solutions are designed to deliver the performance and efficiency required to enable the cloud-to-edge infrastructure for a world with a trillion connected devices,” said Mohamed Awad, vice president of marketing, Infrastructure Line of Business, Arm. “Our collaboration with Moortec on the N1 SDP test chip demonstrates how another piece of validated IP fits within the Neoverse platform, accelerating development and adoption of Arm-based solutions across the infrastructure.”
“Through our collaboration, we are helping to enhance performance and efficiency of Arm’s next-generation compute technology on 7nm. By contributing our high accuracy embedded sensing fabric to the development of the Neoverse N1 SDP, we’re enabling customers to benefit from higher performance and reliability within machine learning, artificial intelligence and data analytics applications,” said Moortec CEO, Stephen Crosher.
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