Synopsys 3DIC Compiler Enables Samsung Tapeout of Advanced Multi-die Packaging of High-Bandwidth Memories for HPC Applications

Comprehensive Design and Analysis Capabilities Extend Moore’s Law for SoCs Through Samsung’s Multi-die Integration

Synopsys, Inc. announced that its 3DIC Compiler solution enabled Samsung Foundry to design, implement and tape out a complex 5-nanometer SoC featuring eight high-bandwidth memories (HBMs) in a single package. With 3DIC Compiler, Samsung’s multi-die integration (MDI), based on silicon interposer technology, was able to scale complexity and capacity of new SoC designs for high-performance computing (HPC) applications. The collaboration with 3DIC Compiler accelerated Samsung’s design productivity and reduced turnaround time from months to hours.

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Advanced packaging has become increasingly important to address key design challenges in accelerating markets, such as HPC, which is driving the growing number of HBMs integrated in a package for higher bandwidth and faster access. With each HBM stack integration, thousands of additional die-to-die interconnects are required, increasing the design complexities of a multi-die system in a package and the need for extensive analysis from early exploration to design signoff.

“AI and high-end networking applications increasingly require higher levels of integration, high-performance computing and increased memory access – all driving the demand for advanced-packaging technologies,” said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. “Samsung’s innovative MDI silicon interposer technology enables customer innovation with greater functionality and enhanced system performance while allowing smaller form factors and faster time to market. Our collaboration with Synopsys provides customers with a comprehensive co-design and co-analysis solution for designing with Samsung’s MDI technologies ensuring high productivity and faster time to production.”

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Synopsys’ 3DIC Compiler is built on a unified platform that leverages signal integrity-aware automated routing and shielding capabilities for co-design efficiency. 3DIC Compiler provides a comprehensive set of features for design automation, including bump placement, high-density routing and shielding. To ensure design robustness, 3DIC Compiler also provides in-design support of the Ansys RedHawk family of chip-package co-simulation tools for a comprehensive analysis of signal and power integrity, and thermal reliability for large numbers of HBM stacks in a package using Samsung’s silicon interposer technology.

“SoC teams face complex design challenges when developing heterogenous designs using multi-die solutions for leading-edge applications including HPC, AI, 5G and automotive,” said Charles Matar, senior vice president of System Solutions and Ecosystem Enablement for the Design Group at Synopsys. “Our work with Samsung provides an optimal ecosystem for advanced levels of integration and technological innovation, resulting in a faster time to market, solving complex architectures and improved system level cost for our customers.”

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