Synopsys 3DIC Compiler Qualified for Samsung Foundry’s Multi-Die Integration Flow, Accelerating 2.5D and 3D Designs
Mutual Customers Gain Full Exploration-to-Signoff 3DIC Solution to Manage Complexity of Hundreds of Billions of Transistors
To strengthen innovation of complex SoCs for compute-intensive applications such as high-performance computing, AI and 5G, Synopsys, Inc. announced that its 3DIC Compiler unified 2.5D and 3D multi-die package co-design and co-analysis platform has been qualified for Samsung Foundry’s Multi-Die Integration flow. As a result, mutual customers will be able to productively manage the complexities of 2.5D and 3D designs, while benefiting from power, performance and area (PPA) advantages and scalability to support hundreds of billions of transistors via a single 3DIC platform.
“Together, Synopsys and Samsung Foundry are easing the way to optimized multi-die designs through early to full system implementation and signoff analysis,” said Sangyun Kim, vice president of Foundry Design Technology Team at Samsung Electronics. “Co-design and co-analysis of silicon and advanced packages with Synopsys’ 3DIC Compiler platform is another example of how our close collaboration results in advanced productivity solutions that reduce turnaround time and costs for our mutual customers.”
Multi-die integration —in which many chip dies are stacked and integrated in a single package—are growing in popularity as a means to meet system specifications in terms of PPA, functionality, form factor and cost. They provide end-product modularity and flexibility to mix and match separate technologies into solutions addressing different market segments or needs. 3DIC Compiler is a complete, end-to-end solution for efficient multi-die design and full-system integration. It is built on the common, scalable data model of the highly integrated Synopsys Fusion Design Platform™, and enables multi-die integration co-design and co-analysis to provide a single, hyper-convergent environment for 3D visualization, pathfinding, exploration, design, implementation, analysis and signoff.
“The 3D workflow has traditionally been extremely fragmented and iterative, with multiple tools and flows needed to achieve multi-die system integration, thus limiting engineering productivity. Meeting our customers’ needs for greater efficiency and scalability, our pathbreaking innovations in 3DIC Compiler have carved out a lead in 3D silicon realization by delivering a single platform from exploration to signoff,” said Shankar Krishnamoorthy, GM and corporate staff for the Silicon Realization Group at Synopsys. “Samsung and Synopsys have worked closely to validate 3DIC Compiler for the foundry’s MDI flow, providing our mutual customers with a tapeout-proven platform to optimize their innovative multi-die designs and get to market quickly.”
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The 3DIC Compiler platform integrates multi-die, extraction and static timing analysis (STA) with StarRC™ and PrimeTime® golden-signoff solutions; electromigration/IR drop (EMIR), signal integrity/power integrity (SI/PI) and thermal analysis with Ansys® RedHawk™-SC and HFSS technologies; circuit simulation with PrimeSim™ Continuum; IC Validator™ design rule checking (DRC) and layout vs. schematic (LVS); and Synopsys TestMAX™ IEEE1838 multi-die design-for-test (DFT) solution.
3DIC Compiler is part of the broader Fusion Design Platform and, combined with Fusion Compiler™, enables expansive, multi-die, RTL-to-GDSII co-optimization. In addition, the solution offers DesignWare® Foundation, 112G USR/XSR Die-to-Die and HBM2/2E/3 IP, SiliconMAX™ In-Chip Monitoring and Sensing IP and support for integrated photonics. The broader solution provides hardware and software co-verification, power analysis and system physical prototyping with the Synopsys Verification Continuum® Platform. Both the 3DIC Compiler platform and the broader silicon realization portfolio are part of the Synopsys Silicon to Software™ strategy, enabling the development of semiconductor and software products for tomorrow’s realities.
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