Synopsys and TSMC Accelerate 2.5D/3DIC Designs With Chip-on-Wafer-on-Substrate and Integrated Fan-Out Certified Design Flows
Synopsys 3DIC Compiler platform reduces design turnaround time for chip-package co-design implementation
Synopsys, Inc. announced that Synopsys and TSMC have collaborated to deliver certified design flows for advanced packaging solutions using the Synopsys 3DIC Compiler product for both silicon interposer based Chip-on-Wafer-on-Substrate (CoWoS-S) and high-density wafer-level RDL-based Integrated Fan-Out (InFO-R) designs. 3DIC Compiler provides packaging design solutions required by today’s complex multi-die systems for applications like high-performance computing (HPC), automotive and mobile.
“Applications such as AI and 5G networking increasingly require higher levels of integration, lower power consumption, smaller form factors, and faster time to production, and this is driving the demand for advanced-packaging technologies,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “TSMC’s Innovative 3DIC technologies such as CoWoS and InFO enable customer innovation with greater functionality and enhanced system performance at increasingly competitive costs. Our collaboration with Synopsys provides customers with a certified solution for designing with TSMC’s CoWoS and InFO packaging technologies to enable high productivity and faster time to functional silicon.”
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The Synopsys 3DIC Compiler solution provides a unified chip-package co-design and analysis environment for creating an optimal 2.5D/3D multi-die system in a package. The solution includes features such as TSMC design macro support and auto-routing of high-density interposer based interconnects using CoWoS technology. For RDL-based InFO designs, schedules are reduced from months to a few weeks through automated DRC-aware, all-angle multilayer signal and power/ground routing, power/ground plane creation, and dummy metal insertion, along with the support for TSMC design macros.
For CoWoS-S and InFO-R designs, dies need to be analyzed in the context of the package and the overall system. Die-aware package and package-aware die power integrity, signal integrity, and thermal analysis are critical for design validation and signoff. Integration of Ansys’ RedHawk family of chip-package co-analysis solutions in 3DIC Compiler meets this critical need, enabling seamless analysis and faster convergence to an optimal solution. Customers can achieve smaller designs and higher performance by eliminating overdesign.
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“Synopsys and TSMC recognize the design challenges being faced by our customers looking to create next-generation products using multi-die solutions, and our collaboration provides our mutual customers with an optimized path to implementation,” said Charles Matar, senior vice president of System Solutions and Ecosystem Enablement for the Design Group at Synopsys. “By providing natively implemented silicon interposer and fan-out layouts, physical verification, co-simulation and analysis capabilities in a single unified platform, we enable our customers to address today’s complex architectures and packaging requirements, in addition, to increased productivity and faster turnaround time.”
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