Microchip Introduces New CXL Smart Memory Controllers for Data Center Computing Enabling Modern CPUs to Optimize Application Workloads

The SMC 2000 family delivers DDR memory bandwidth and capacity expansion, reliability, media flexibility for next-generation CPUs and SoCs to accelerate AI and machine learning performance

 The continuous computational demands of artificial intelligence (AI) and machine learning (ML) workloads, cloud computing and data analytics deployed on traditional parallel attached memory have reached an efficiency plateau due to the limitations of increased memory channels on a processor. Microchip Technology Inc. announces the expansion of its serial-attached memory controller portfolio with the new SMC 2000 series of Compute Express Link (CXL) based Smart Memory Controllers that enable CPUs, GPUs and SoCs to utilize CXL interfaces to connect either DDR4 or DDR5 memory. This solution delivers more memory bandwidth per core, more memory capacity per core, and lowers the overall total cost of ownership in the data center by allowing modern CPUs to optimize application workloads.

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The low-latency SMC 2000 16x32G and SMC 2000 8x32G memory controllers are designed to CXL 1.1 and CXL 2.0 specifications, DDR4 and DDR5 JEDEC standards and support PCIe^® 5.0 specification speeds. The SMC 2000 16x32G is the industry’s highest-capacity controller with 16 lanes operating at 32 GT/s and supports two channels of DDR4-3200 or DDR5-4800, resulting in a significant reduction in the required number of host CPU or SoC pins per memory channel.

Typical CXL attached memory modules include 512 GB of memory or more, providing an effective mechanism to increase the memory bandwidth available to processing cores. This new paradigm shift provides data center operators the ability to deploy a broader range of ratios for memory to CPU cores depending on their actual application needs, resulting in improved memory utilization and lower Total Cost of Ownership (TCO).

“Microchip is excited to introduce our first CXL-based serial memory controller device to the market,” said Pete Hazen, corporate vice president of Microchip’s Data Center Solutions business unit. “We identified CXL as a disruptive technology early on and were integral to the standard’s definition. Microchip’s continued presence in the memory infrastructure market underscores our commitment to improving performance and efficiency for a broad range of SoC applications to support the increasing memory requirements of high-performance data center applications.”

“The CXL Consortium was founded with a vision to deliver to the industry an open standard that would accelerate next-generation data center performance,” said Siamak Tavallaei, president, CXL Consortium. “We’re pleased to see Microchip, a valuable contributor to the CXL Consortium, deliver a CXL solution enabling a new ecosystem for high-performance, heterogeneous computing.”

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Microchip’s SMC 2000 CXL-based memory controllers employ an innovative design that delivers  Reliability, Availability and Serviceability (RAS) features to transform solutions to the next level of efficiency and performance. Through CXL connectivity, the SMC 2000 external memory controller enables a CPU or SoC to utilize a broad set of media types with different cost, power and performance metrics without having to integrate a unique memory controller for each different type. For example, using an SMC 2000 controller with DDR-4 memory, advanced CPUs that only directly support DDR5 can now also re-use DDR-4 memory expansion. The dual signature authentication and Trusted Platform support, secure debug, and secure firmware update ensure the SMC 2000 CXL-based controller family also meets all critical storage and enterprise application security needs.

Data center application workloads require future memory products that can deliver the same high-performance bandwidth, low latency and reliability of today’s parallel-DDR based memory products. The CXL platform is one of the biggest industry disruptions in recent years, bringing to market a new standard serial interface for CPUs to expand memory beyond the parallel DDR interface to provide the next level of efficiency and performance to the data center.

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