Astera Labs Welcomes Establishment of New UCIe Chiplet Interconnect Standard

Plans to leverage PCIe® and CXL™ connectivity expertise to enable emerging Universal Chiplet Interconnect Express ecosystem

Astera Labs, a pioneer in connectivity solutions for intelligent systems, welcomes the establishment of Universal Chiplet Interconnect Express (UCIe), an open industry standard that offers high-bandwidth, low-latency, power-efficient, and cost-effective connectivity between chiplets at the package level. The UCIe 1.0 Specification covers the die-to-die I/O physical layer, die-to-die protocols, and software stack, leveraging the well-established PCI Express® (PCIe®) and Compute Express Link™ (CXL™) industry standards.

“We are excited to support this new industry effort with our proven expertise in intelligent CXL and PCIe interconnects and look forward to expanding our purpose-built connectivity solutions portfolio to include products based on the UCIe standard.”

“The new UCIe specification enables innovative chiplet solutions to optimize power, performance, cost, and time to market of large SoCs for data centers as well as enhanced resource sharing and pooling across servers,” said Jitendra Mohan, CEO, Astera Labs. “We are excited to support this new industry effort with our proven expertise in intelligent CXL and PCIe interconnects and look forward to expanding our purpose-built connectivity solutions portfolio to include products based on the UCIe standard.”

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The UCIe specification defines the complete standardized die-to-die interconnect and compliance testing that will enable end users to easily mix and match chiplet components from a multi-vendor ecosystem for System-on-Chip (SoC) construction, including customized SoCs. ​

“UCIe is the culmination of learnings over many years implementing on-package interconnects and the time is right for industry standardization,” said Dr. Debendra Das Sharma, Intel Senior Fellow. “We are excited that Astera Labs is joining the consortium and working to develop products such as UCIe Retimers and UCIe Memory Accelerators.”

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