Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process
Cadence Design Systems, unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, switch fabric system-on-chips (SoCs) and 5G wireless infrastructure. The extended long-reach SerDes PHY supports insertion loss (IL) of 43db with BER of 10e-7—thereby providing additional performance margin beyond the standard long-reach specifications—and enables exceptional system robustness for lossy and reflective channels observed in open box platforms as well as lengthy direct attach copper (DAC) cables.
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“Our next-generation 112G-ELR SerDes on TSMC N4P solution offers exceptional performance margin and system robustness for customer applications”
The Cadence® 112G-ELR SerDes PHY IP on TSMC’s N4P process, a performance-focused enhancement of the TSMC 5nm technology platform, incorporates industry-leading digital signal processor (DSP)-based SerDes architecture with maximum likelihood sequence detection (MLSD) and reflection cancellation technology. The SerDes PHY IP is compliant with IEEE and OIF Long-Reach (LR) standards while providing extra performance margin for ELR applications. The optimized power, performance and area are ideal for different user scenarios, including high port-density applications. In addition to ELR and LR channels, the IP also supports Medium Reach (MR) and Very Short Reach (VSR) applications with a flexible power-saving capability over different channels. The supported data rates range from 1G to 112G with NRZ and PAM4 signaling, enabling reliable high-speed data transfer over backplane, direct-attached cable (DAC), chip-to-chip and chip-to-module channels.
“Cadence’s latest 112G-ELR IP on TSMC’s N4P process will benefit our mutual customers with significant performance improvement in silicon, helping them address design challenges with the continuous technology advancement from Cadence’s leading IP solutions and TSMC’s advanced process technologies,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Our latest collaboration with Cadence promotes the development of new technologies for hyperscale, AI/ML, 5G infrastructure and other applications.”
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“Our next-generation 112G-ELR SerDes on TSMC N4P solution offers exceptional performance margin and system robustness for customer applications,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “Our close collaborations with leading hyperscale and data center customers have given us insight into the stringent industry requirements, resulting in enhanced architecture that offers improvements on all key parameters for 112G SerDes. Our 112G-ELR SerDes solution on TSMC’s N4P process further solidifies our leadership position with high-performance connectivity IP offerings for hyperscale data centers, and customers can also enjoy the benefits associated with the TSMC N4P process technology.”
Cadence currently has the 112G-ELR on TSMC N4P test chip silicon in-house, demonstrating optimal performance. The Cadence 112G-ELR SerDes solution on TSMC’s N4P process is available for broad customer engagements now. Cadence has built a large customer base for its PAM4 SerDes by enabling different variations. The 112G-ELR SerDes PHY IP on TSMC’s N4P process is part of the broader Cadence IP portfolio and supports the Cadence Intelligent System Design™ strategy, which enables advanced-node SoC design excellence
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