Chiplet Summit Promotes Higher Design Productivity at Leading-Edge Nodes

Chiplet Summit, to be held January 24-26 at the DoubleTree by Hilton San Jose Hotel, will help designers go-to-market faster by using the latest design architecture – chiplets. All the leading semiconductor companies are now using them to speed up design at leading-edge process nodes. The Summit will help designers with the new stage of heterogeneous integration and the new requirement of implementing a die-to-die interface. It will also help them divide up designs properly, add design-for-test and design-for-manufacturing features, and implement both chiplet-level and package-level debug and test. Furthermore, it will offer insight into chiplet markets, packaging, and data management.

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“Chiplet Summit focuses on bringing the entire chiplet ecosystem together, including designers, packagers, testers, and specialists in integration, interfaces, security, power, and thermals. They must work together throughout the development process to produce successful chips that foundries can manufacture at low cost”

The event covers the latest architectures, development methods, and applications. Expert panels will discuss best choices, likely breakthroughs, and long-term trends. Industry-leading keynotes give designers essential information about trends and roadmaps. Speakers represent Intel, Applied Materials, Corigine, proteanTecs, Silicon Catalyst (discussing the $60B US CHIPS Act), and Open Compute Project (OCP).

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“Chiplet Summit focuses on bringing the entire chiplet ecosystem together, including designers, packagers, testers, and specialists in integration, interfaces, security, power, and thermals. They must work together throughout the development process to produce successful chips that foundries can manufacture at low cost,” said Chuck Sobey, Summit General Chair.

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