GBT Integrated Circuit’s Geometrical Design Rule Automatic Correction Patent, Received a Notice of Allowance

GBT Technologies received a notice of allowance for its nonprovisional patent application for integrated circuits (IC) geometrical design rule automatic correction system and method, internal code name Omega. The patent protects a technology for automatic correction of geometrical design rule violations within an integrated circuit’s layout. IC layout Design Rule Check (DRC) correction is the process of identifying and rectifying geometrical violations in the layout design of an IC to comply with the manufacturing process design rules.

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Design rules define the physical constraints and limitations for creating microchip’s layouts, ensuring manufacturability and functionality. Typically, this type of DRC correction is done manually and takes a considerable amount of time to perform. The invention describes system and methods for automatic correction of IC’s layout without any manual intervention, maintaining its electrical connectivity and keeping compliance with design for manufacturing (DFM) and Reliability Verification (RV) constraints. When an IC layout is created, it undergoes a DRC verification process to check for violations against the specified design rules. These violations can include geometrical errors, such as spacing violations, overlapping, or incorrect widths, which can affect the performance, functionality and reliability of the IC. Particularly in advanced nanometer nodes of 5nm and below, a manual design rule correction may take a significant amount of time and increases the overall project’s design time.

The goal of the Omega invention is to perform the correction within minutes using Artificial Intelligence neural network algorithms. The described technology performs DRC Analysis where the layout is analyzed to identify design rule violations. The DRC tool checks the layout against rules related to dimensions, spacing, proximity, alignment, and similar. After violation Identification, a report is generated, highlighting the violations found in the layout. Each violation is categorized based on its severity, such as errors that must be fixed (hard violations) or warnings that might affect performance (soft violations). The system then reviews the DRC report to understand the nature, location and the implications of the violations. This involves analyzing the design and identifying the specific layout elements causing the violations.

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The technology operates according to Machine Learning-driven, automatic correction strategies. Based on the identified violations, the technology formulates strategies to rectify the errors. This can involve adjusting the layout geometry, modifying the placement of components, resizing or repositioning polygons or making other layout changes. The patent describes a capability to perform a full hierarchical correction throughout the microchip’s sub-blocks considering electrical and manufacturing aspects. As the number and complexity of IC’s design rules have been dramatically increased over the recent decade especially in small scale nanometer nodes of 7nm and below, it creates a bottleneck to maintain reasonable timelines, meeting release schedules and achieving desired semiconductor’s cost. The invention seeks to solve this crisis by providing an automation technology to correct design rule violations with a click-of-a-button, improving the design’s quality and electrical characteristics, enabling the design and manufacturing of better chips with higher silicon yield, faster. GBT plans to continue its R&D efforts in this domain introducing further innovative advancements in the field in the upcoming years.

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