Synopsys IC Compiler II Delivers First-Pass Silicon Success for Graphcore’s Multi-Billion Gate AI Processor
Innovative AI-Hardware Design Technologies Accelerate Time-to-Market for Second-Generation 7nm Colossus IPU
Synopsys, Inc. announced that Graphcore achieved first-pass silicon success using the industry-leading IC Compiler II place-and-route solution, part of the Synopsys Fusion Platform, for designing its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), featuring 59.4 billion transistors, on an industry-leading 7nm advanced process technology. Graphcore leveraged Synopsys IC Compiler II ultra-high capacity architecture and innovative technologies for AI-hardware design resulting in an accelerated implementation of their massive AI processor. Synopsys’ RTL-to-GDS flow with state-of-the-art power optimization capabilities along with embedded golden signoff technologies like PrimeTime delay calculator, provided Graphcore design teams superior out-of-the-box PPA metrics, and the fastest design closure.
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“Synopsys’s digital full-flow solution with its best-in-class RTL-to-GDS tools, including Design Compiler and IC Compiler II, offers the most comprehensive single-vendor platform, critical to the on-schedule tape out of our latest Colossus IPU,” said Phil Horsfield, vice president of Silicon at Graphcore. “Our long-standing relationship with Synopsys has enabled us to leverage state-of-the-art technologies from IC Compiler II and exceed the performance/power targets of this advanced AI processor. We are confident that continued collaboration with Synopsys on IC Compiler II and Fusion Compiler will enable us to push the boundaries of machine intelligence compute.”
The second-generation Colossus GC200 IPU from Graphcore is a sophisticated chip, integrating 1,472 independent processor cores and more than 900 megabytes of on-chip memory to deliver superior parallel processing power for data-center scale AI applications. Synopsys’ IC Compiler II, with its AI-design focused capabilities, includes top-level interconnect planning, logic restructuring, congestion-driven mux optimization and full-flow concurrent clock and data optimization delivers best-in-class PPA for the highly repetitive, MAC-based topologies typical in complex AI accelerator chips. Further, its native, high-capacity data model with adaptive abstraction and distributed implementation can efficiently handle multi-billion instance designs with quick turn-around-time. With a unique, golden signoff engine backbone, IC Compiler II delivers highest correlation and hyper-convergent design, to further accelerate design turnaround time.
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“The design complexity boundaries of AI compute are continuing to be pushed to its limits, such as with Graphcore’s introduction of its latest Colossus IPU,” said Neeraj Kaul, vice president of Engineering, Design Group at Synopsys. “Its success in leveraging the latest, AI-optimized technologies in IC Compiler II to simultaneously meet the multiple aggressive design targets for their most complex chip reinforces our leadership position as the place-and-route tool of choice for next-generation, AI designs.”