Alchip Provides Supercomputer Processor Design Support
PFN’s MN-3 ranked in 1st place of Green500
Alchip Technologies, Limited, the high-performance computing ASIC leader, revealed that it assisted Preferred Networks, Inc., the Japanese leader in deep learning technology, with the development of that company’s ground-breaking MN-3 supercomputer.
The MN-3, powered by the MN-Core deep learning processor, recently won 1st place in the June 2020 Green500 ranking of the world’s most energy-efficient supercomputers. Green500 rankings are published semi-annually by the non-profit Top500 rating service.
MN-Core is a deep learning processor jointly developed by PFN and Kobe University. Alchip’s advanced LSI design technology helped achieve the required device performance. MN-Core is at the leading edge of machine learning with an approx. 800mm sq. per die, designed as an advanced power saving 4-die multi-chip package that incorporates Alchip’s proprietary die-to-die interface technology. Alchip executed the ASIC’s physical design, trial manufacturing and production.
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MN-Core is optimized for matrix operations, a type of computation characteristic of deep learning. It achieves world-class energy efficiency of 1 TFLOPS (half-precision) per watt. MN-3 has four this MN-Core processor. To win first place in the Green500 rankings, PFN operated 40 nodes (total 160 MN-Core) that reached 21.11GFLOPS/W.
“Because the MN-Core is a complex, full reticle sized SoC, it creates a number of design challenges. Chief among them is providing heat dissipation for the enormous 500-watt power consumption,” explained Johnny Shen, CEO, Alchip Technologies. “We also developed mechanical package samples at the very early stage to eliminate the reliability concerns of mounting such a large chip. This complicated test design was a particularly challenging, given the project’s tight schedule,” he explained.
The high- performance computing ASIC is built on TSMC’s process technology. Each die hosts 512 processor core engines. It was designed using Alchip’s unique clock tree methodology to achieve the required low-power specs.
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The four-in-one 6,400~-ball stacked package is arranged on an organic substrate measuring 85x85mm2. It incorporates Alchip’s proprietary D2D (die-to-die) interface technology that provides the bandwidth demand within a small area/power ratio. Alchip provided total chip and package integration and verification.
“Alchip’s leading-edge design technology contributed greatly to the development of PFN’s MN-3 supercomputer and its deep learning performance, especially through their high-density, low-voltage implementation of the matrix computation units,” Yusuke Doi, Preferred Networks’ Vice President of Computing Infrastructure, explained. “We will continue our research and development in deep learning using MN-Core which Alchip supported us to develop.”
“As PFN’s foundry partner, TSMC is deeply honored to be part of this joint R&D project with PFN and Alchip, and support PFN’s hardware strategy to promote the practical application of Japan’s R&D in deep learning technology and related technologies. We look forward to seeing outstanding achievements from the further acceleration of PFN’s research in deep learning and related technologies,” said Makoto Onodera, President of TSMC Japan.
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