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Semisrael 2018: Esilicon to Present on IP Platforms for AI and High-Performance Networking ASCIs

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7nm 56g DSP Serdes Demos and Private Meetings Available

eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will present its two new 7nm IP platforms at SemIsrael on 27 November 2018 in Airport City, Israel. eSilicon will also demonstrate its 7nm 56G full-DSP SerDes in booth 42.

SerDes Demonstrations: Booth 42
Using Samtec ExaMAX® Backplane Connector paddle cards and an ExaMAX Backplane Cable Assembly, eSilicon will demonstrate the performance, flexibility and extremely low power consumption of its 7nm, 56G PAM4 and NRZ DSP-based long-reach SerDes. Error-free operation (without the need for forward error correction) will be showcased across multiple channels, operation frequencies and modulation schemes, thanks to a very powerful and programmable real-time DSP-based equalization capability. Bit-error rate, eye diagram monitors and pulse response processing will be shown among many other capabilities.

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An IP Platform for High-Performance Networking ASICs
IP & Cores Track 11:40 – 12:00
David Axelrad, Senior Director, IP Marketing, eSilicon
eSilicon’s 7nm IP platform delivers a complete ecosystem of networking-optimized IP with high configurability designed in. All IP in the platform is “plug and play,” using the same metal stack, reliability requirements, operating ranges, control interfaces and DFT methodology. This configurability and compatibility results in better performance, higher density and faster time to market.

The platform includes high-performance, extremely flexible 56G and 112G SerDes, a ternary CAM (TCAM) compiler, a robust and programmable high-bandwidth memory (HBM2) PHY, multiple network-optimized memory compilers and extended-voltage general-purpose and LVDS I/O libraries.

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An IP Platform for AI ASICs
AI & Machine Learning Track 2:00 – 2:20
Pierre Boyer, Sales and Applications Manager, eSilicon
The neuASIC™ IP platform for AI ASICs includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators for AI and ML ASICs. The platform includes an array of compiled, hardened and verified functions and also provides a software AI accelerator builder function that provides power/performance/area (PPA) estimates of the chosen ASIC architecture before RTL development starts.

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