Artificial Intelligence | News | Insights | AiThority
[bsfp-cryptocurrency style=”widget-18″ align=”marquee” columns=”6″ coins=”selected” coins-count=”6″ coins-selected=”BTC,ETH,XRP,LTC,EOS,ADA,XLM,NEO,LTC,EOS,XEM,DASH,USDT,BNB,QTUM,XVG,ONT,ZEC,STEEM” currency=”USD” title=”Cryptocurrency Widget” show_title=”0″ icon=”” scheme=”light” bs-show-desktop=”1″ bs-show-tablet=”1″ bs-show-phone=”1″ custom-css-class=”” custom-id=”” css=”.vc_custom_1523079266073{margin-bottom: 0px !important;padding-top: 0px !important;padding-bottom: 0px !important;}”]

Tenstorrent and Movellus Form Strategic Engagement for Next-Generation Chiplet-Based AI and HPC Solutions

Movellus_Wordmark.png

Enabling Cross-Foundry IP for Power and Performance Optimization

Movellus and Tenstorrent announced that Tenstorrent has licensed Movellus’ digital IP family as part of a strategic engagement, for its AI and HPC chiplet solutions. This collaboration aims to leverage the strengths of both companies to develop chiplet-based solutions that enhance performance while optimizing power consumption. Movellus Aeonic Digital IP allows Tenstorrent to leverage advanced clocking techniques to reduce overall energy consumption.

Also Read: Humanoid Robots And Their Potential Impact On the Future of Work

“By collaborating with Movellus and integrating their technology, we are optimizing power efficiency in our processors and continuing to drive Tenstorrent’s leadership in scalable AI chiplets,” said Keith Witek, Chief Operating Officer of Tenstorrent.

Related Posts
1 of 40,789

Movellus’ Aeonic portfolio offers products designed to tackle critical infrastructure challenges in modern computing, such as on-die sensing, digital clocking, and power delivery. Notably, the digital adaptive clocking family facilitates architectural advancements like per-core distributed clocking and fine-grained dynamic frequency scaling (DFS). Additionally, when coupled with droop detectors, these products provide advanced clock management capabilities, allowing for Vmin reduction by effectively mitigating droop while minimizing any performance impact. With these products it is possible to combine localized clocking, DFS, DVFS, and droop mitigation in a unified solution, simplifying design and easing integration.

“Movellus’ digital clocking technology enables us to distribute digital PLLs across our chip to provide a localized, fine-grained clocking, something that is not possible with traditional analog PLLs,” said Michael Smith, Senior Director of SoC Hardware Engineering at Tenstorrent. “In addition, their process agnostic digital architecture provides a cohesive software interface across multiple devices.”

Also Read: Unilever and Accenture Join Forces to Establish a New Industry Standard in Generative AI-Powered Productivity

“Tenstorrent is pioneering AI and HPC compute with their novel and scalable hardware architectures and software stack,” said Mo Faisal, CEO of Movellus. “We are grateful to be a part of this ground-up approach that is foundational to the advancement of AI and HPC compute with an intention of maximizing energy efficiency – a much-needed development in the age of AI.”

[To share your insights with us as part of editorial or sponsored content, please write to psen@itechseries.com]

Comments are closed.