Xilinx Brings Breakthrough To Vivado Design Tools With State-Of-The-Art Machine-Learning Optimization For Accelerated Designs

Delivers an average 5x reduction in compile time and 10% improvement in quality of results

Xilinx, Inc. introduced Vivado® ML Editions, the industry’s first FPGA EDA tool suite based on machine-learning (ML) optimization algorithms, as well as advanced team-based design flows, for significant design time and cost savings. Vivado ML Editions delivers 5x faster compile time and breakthrough quality of results (QoR) improvements on average 10% for complex designs, compared to the current Vivado HLx Editions.

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“Today’s EDA designers are challenged by ever-increasing design complexity. Machine-learning is the next big leap forward for accelerating the design process and delivering QoR gains,” said Nick Ni, director of marketing, Software and AI Solutions at Xilinx. “Vivado ML will help developers slash design cycles and deliver new levels of productivity from design creation to closure.”

ML-based optimization

Vivado ML Editions enables ML-based algorithms that accelerate design closure. The technology features ML-based logic optimization, delay estimation and intelligent design runs, which automates strategies to reduce timing closure iterations.

“The new Vivado ML Editions’ intelligent design runs is a game changer,” said Robert Atkinson, principal hardware engineer, National Instruments. “By offering a push-button method for aggressively improving timing results, it generates QoR suggestions that bring maximum impact and deliver expert quality results with a reduction in user analysis – especially for tough-to-close designs.”

Faster compile time and team-based productivity

Xilinx is also introducing the concept of an Abstract Shell, which allows users to define multiple modules within the system to be compiled incrementally and in parallel. This enables an average compile time reduction of 5x and, up to 17x, compared to traditional full system compilation. Abstract Shell also helps protect a customer’s IP by hiding the design details outside of the modules, critical for applications like FPGA-as-a-Service and value-added system integrators.

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In addition, Vivado ML Editions improves collaborative design with Vivado IP Integrator, which enables modular design using the new “block design container” feature. This capability promotes a team-based design methodology and allows for a divide-and-conquer strategy to handle large design with multisite cooperation.

Unique adaptability features like Dynamic Function eXchange (DFX) to enable more efficient use of silicon resources by loading custom hardware accelerators, dynamically at runtime over-the-air. With the ability of DFX to load design modules in a few milliseconds, it opens up new use cases such as a car swapping different vision algorithms during processing of a frame, or a genomic analysis swapping different algorithms in real-time as it sequences DNA.

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