Synopsys and Samsung Foundry Enable 3nm Process Technology for Power- and Performance-Demanding Mobile, HPC and AI Designs

To drive adoption of Samsung’s 3nm gate-all-around (GAA) technology for designs requiring optimal power, performance and area (PPA), Synopsys, Inc. announced that its longstanding collaboration with Samsung Foundry has produced multiple successful test chip tapeouts on Synopsys digital and custom design tools and flows, certified for Samsung Foundry’s most advanced process. Mutual customers using Samsung Foundry’s SF3 technology can benefit from the approximately 50% reduced power, 30% improved performance and 30% smaller area that the technology node has demonstrated versus the Samsung SF5E process.

“Today’s demanding mobile, high-performance computing and AI applications require power and performance levels that stretch the limits of small geometries,” said Sangyun Kim, corporate vice president of the Foundry Design Technology Team at Samsung Electronics. “Our longstanding collaboration with Synopsys on EDA design flow certifications provides mutual customers with substantial power, performance and area advantages.”

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Collaborating for Continued Silicon Advancements

Synopsys and Samsung Foundry have continued innovating to drive the silicon improvements that our smart, connected world demands. Samsung Foundry streamlined its 3nm process development costs and timeline, efficiently evaluating its process options based on PPA design metrics. The foundry continues to include Synopsys DSO.ai technology in its flow, utilizing the machine learning capabilities to massively scale the exploration of choices in chip design workflows and expedite development of its process.

“Synopsys’ strategic collaboration with Samsung Foundry has enabled us to remain in lockstep through every generation of their process technology advancements,” said Shankar Krishnamoorthy, GM of the EDA Group at Synopsys. “By providing leading EDA design flows certified on the most advanced Samsung 3nm technology, our mutual

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