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Synopsys Announces Industry’s First CXL 2.0 VIP Solution for Breakthrough SoC Performance

Native System Verilog VIP Features Built-in Coverage, Verification Planning, and Memory-Aware Debug and Performance Analysis

Synopsys, Inc. announced the availability of the industry’s first Verification IP (VIP) for Compute Express Link (CXL) 2.0 designed for breakthrough performance in data-intensive system-on-chips (SoCs). CXL is the next-generation open standard interconnect that enables an ecosystem for high-speed communication between the CPU and workload accelerators, such as GPUs, FPGAs and other purpose-built accelerator solutions, as well as memory expansion devices. The technology is built upon the well-established PCI Express® infrastructure, leveraging the PCI Express 5.0 physical and electrical interface.

Synopsys VIP for CXL uses next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables ease of integration within existing verification environments and speeds up simulation performance allowing users to run greater number of tests and accelerate time to first test. VIP for CXL is natively integrated with Synopsys Verdi Protocol and Performance Analyzer and includes built-in coverage and verification plans for faster verification closure. In addition, Synopsys’ silicon-proven DesignWare CXL IP delivers a x16 link for maximum bandwidth with low latency, supporting all three CXL protocols (, CXL.cache, CXL.mem) and device types to meet specific application requirements.

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“Synopsys’ cache coherency verification IP portfolio, including CXL 2.0, CXL 1.1 and CCIX, enables support of emerging applications with massive data throughput requirements,” said Vikas Gautam, Vice President of R&D for the Synopsys Verification Group. “Our growing portfolio of industry-first verification IP and close collaborations with standards organizations and memory vendors enable designers to adopt and integrate the latest interconnect technologies rapidly.”

“The advancement of CXL as an open standard interconnect technology to accelerate next generation data center performance is our singular focus,” said Jim Pappas, Chairman at CXL Consortium. “We appreciate Synopsys’ support of CXL Consortium to help advance the adoption of CXL technology.”

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“Bringing to market the next major interconnect advancement for data intensive applications, such as artificial intelligence, memory expansion, and cloud computing requires a robust ecosystem,” said Dr. Debendra Das Sharma, Intel Fellow and Director I/O Technologies and Standards. “Collaborating with industry-leaders like Synopsys to advance CXL propels the industry forward and enables our customers to meet the performance and data connectivity requirements of their SoCs.”

The CXL 2.0 protocol comes with an increased fan-out, pooling feature set for both physical layer and application layers. New features supported by CXL 2.0 are:

–  CXL switching and support for multiple logical devices (MLD)

–  IDE (security) for both & CXL.cache/mem

–  Ability to negotiate CXL 2.0 devices during APN phase and hot plug, CXL enumeration to view CXL device as PCI Express endpoint

–  Updates for system level manageability through QoS telemetry, function level reset, global persistent flush, memory interleaving and compliance test assertions

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