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Synopsys Announces Industry’s First JEDEC DDR5 Verification IP

Native SystemVerilog VIP Features Built-in Coverage, Verification Planning, and Memory-Aware Debug and Performance Analysis

Synopsys, Inc. announced the availability of the industry’s first JEDEC DDR5 (JESD79-5) compliant Verification IP (VIP) for Double Date Rate 5 (DDR5) DRAM/DIMM. DDR5 is the next-generation standard for random access memory (RAM). The new specification delivers higher performance and lower power for a broad range of enterprise applications, including cloud, IoT, high-performance servers/workstations, hyperscale data centers and big data.

Synopsys VC VIP for DDR5 enables the design and verification of next-generation memory devices with ease-of-use, fast integration, and optimum performance, resulting in accelerated verification closure. In addition, the Synopsys DesignWare® DDR5/4 PHY and Controller IP operating at up to 6400 Mb/s support key features of the DDR5 standard including device size, burst length, DIMM topologies, and reliability, accessibility and serviceability (RAS) features.

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“Bringing to market the next major advancement in mainstream memory architecture requires an ecosystem that offers a broad, diverse set of skills and tools,” said Malcolm Humphrey, vice president of marketing in the Compute and Networking Business Unit at Micron. “Micron’s collaboration with Synopsys on the latest DRAM, NAND and NOR technology enables our customers to develop emerging applications that demand higher-memory bandwidth. The availability of Synopsys’ design-proven DDR5 VIP delivers a new level of confidence to end customers by enabling verification closure of industry-first JEDEC 1.0 DDR5 devices.”

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DDR5 DRAM comes with a significant increase in data rates (3200MT/s to 8400MT/s) and density (8Gb to 64Gb). DDR5 technology is enabled with new performance features to handle high frequency and accuracy requirements, including:

  • An increase to 32 banks and 8 bank groups, BL16, BL32 and BL OTF (16/32)
  • Higher reliability with on die ECC and data CRC for read and write,
  • Enhanced low power capabilities with improved write pattern and lower voltage levels for VDD/VDDQ/VPP and,
  • Enhanced CS training, read training patterns, internal write leveling, CA training and DFE.

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Synopsys VC VIP for DDR5 DRAM/DIMM uses next-generation native SystemVerilog Universal Verification Methodology (UVM) architecture that enables not only ease of integration within existing verification environments but also speeds up simulation performance allowing users to run greater number of tests in given time and accelerate time to first test. VC VIP for DDR5 is natively integrated with Synopsys’ Verdi® Protocol and Performance Analyzer and includes built-in coverage and verification plans for faster verification closure.

“The comprehensive DRAM/DIMM and Flash memory verification IP portfolio from Synopsys, including DDR5/4/3/2, 3DS, MRAM, DDR5 NVDIMM-P, LPDDR5/4, GDDR6, DFI 5.0, HBM2/2E, and SPI/NAND/ONFI, enables support of emerging applications with massive data throughput requirements,” said Vikas Gautam, Vice President of R&D for the Synopsys Verification Group. “By working closely with standard organizations and memory vendors to deliver and deploy first-in-industry customer-proven solutions, we enable designers to adopt the latest memory technologies rapidly.”

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