Rambus Delivers 6400 MT/s DDR5 Registering Clock Driver to Advance Server Memory Performance

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, announced the availability of its new 6400 MT/s DDR5 Registering Clock Driver (RCD) and sampling to the major DDR5 memory module (RDIMM) manufacturers. With a 33% increase in data rate and bandwidth over Gen1 4800 MT/s solutions, the Rambus Gen3 6400 MT/s DDR5 RCD enables a new level of main memory performance for data center servers. Delivering industry-leading latency and power, it offers optimized timing parameters for improved RDIMM margins.

“Data center workloads have an insatiable thirst for greater memory bandwidth and capacity, and our mission is to advance the performance of server memory solutions that meet this need for each new server platform generation,” said Sean Fan, chief operating officer at Rambus. “We were first in the industry to 5600 MT/s, and now we have raised the bar with our Gen3 DDR5 RCD capable of 6400 MT/s to support a new generation of RDIMMs for server main memory.”

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“DDR5 offers tremendous performance enhancements for computing systems,” said Soo-Kyoum Kim, vice president, memory semiconductors at IDC. “As data center applications accelerate demand for more and more memory bandwidth, it is critical that the DDR5 ecosystem extends performance for the fundamental needs of next-generation data centers.”

Rambus DDR5 memory interface chips including the RCD, Signal Presence Detect (SPD) Hub and Temperature Sensors are important in achieving a new level of performance for leading-edge servers. With DDR5 memory, more intelligence is built into the RDIMMs enabling over double the data rate and four times the capacity of DDR4 RDIMMs, while at the same time increasing memory and power efficiency. With over 30 years of high-performance memory experience, Rambus is renowned for its signal integrity (SI) / power integrity (PI) expertise. This expertise helps enable DDR5 memory interface chips delivering superior signal integrity for the command/address and clock signals sent from the host memory controller to the RDIMMs.

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