CEVA Announces its Most Powerful and Efficient DSP Architecture to Date, Addressing the Massive Compute Requirements of 5G-Advanced and Beyond
Mobile World Congress CEVA, the leading licensor of wireless connectivity and smart sensing technologies and co-creation solutions,announced its 5th generation CEVA-XC DSP architecture and its most efficient to date, the CEVA-XC20.
Extending the company’s leadership in DSPs, the new CEVA-XC20 is based on a groundbreaking vector multi-threaded massive compute technology that is designed to address next-generation 5G-Advanced workloads across a broad spectrum of use cases, including smartphones, high-end Enhanced Mobile Broadband (eMBB) devices (e.g. Fixed Wireless Access and Industrial Terminals) and a range of cellular infrastructure devices (e.g. base stations, virtualized DU accelerators, and beamforming compute in Massive MIMO radios). SoC and ASIC designers incorporating the CEVA-XC20 architecture can avail of its industry-leading power efficiency to design greener processors that are smaller and lower power, that in turn have a direct positive impact on the environment and society.
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Dimitris Mavrakis, Senior Research Director, ABI Research, commented: “CEVA’s latest DSP architecture raises the bar for performance and power efficiency in 5G-Advanced cellular baseband processing, adopting a unique multi-thread scheme to address the challenging power, performance and area constraints when dealing with complex 5G scenarios. The CEVA-XC20 offers a compelling solution to any wireless semiconductor or OEM developing their own 5G-Advanced silicon, and can play a critical role in helping customers to address their sustainability goals in the process.”
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The CEVA-XC20 architecture was designed in consultation with CEVA’s leading Tier 1 OEM customers, with the common aim of improving mobile network performance and power efficiency. The CEVA-XC20 solves the performance challenges posed by next-generation compute-intense 5G-Advanced by employing a novel Dynamic Vector Threading (DVT) scheme, which supports true hardware multi-threading, which up until now was only found in general purpose CPU architectures. DVT enables optimal sharing of vector resources between different execution units, resulting in an unprecedented vector utilization efficiency boost. This technique achieves optimal utilization of the VLIW architecture and improves core efficiency for common 5G execution kernels, as well as significantly enhancing use cases involving multi-component carriers and multi-execution tasks. This enables increasing the length of the vector processing units, usually consuming the bulk of the area in vector DSPs, while maintaining and even improving the execution efficiency relative to previous generations.
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