PLDA Announces the Successful CXL Interoperability with Pre-Production Intel Xeon CPU, Code Named Sapphire Rapids

PLDA XpressLINK CXL Controller IP combines the industry’s lowest latency implementation with an easy-to-integrate design, accelerating adoption of CXL in SoC designs.

PLDA, the industry leader in high-speed interconnect solutions, announced the successful CXL interoperability with pre-production Intel Xeon processors code named Sapphire Rapids. The session was conducted at Intel’s Industry Enabling Labs as part of a long-term collaboration between PLDA and Intel’s industry enabling group. It resulted in demonstrated interoperability between PLDA’s XpressLINK CXL IP, running on a PLDA FPGA-based add-in card, and Intel’s development platform equipped with pre-production “Sapphire Rapids” processors.

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PLDA XpressLINK controller implements the CXL.io, CXL.cache, and CXL.mem sub-protocols as specified in the recently released CXL 2.0 Specification, and is already being designed-in at leading technology companies.

According to Stephane Hauradou, CTO at PLDA “Today’s demonstration of interoperability between PLDA’s XpressLINK CXL IP, which delivers the lowest latency in the industry, and a cutting edge CPU like pre-production Intel Sapphire Rapids processor, is a critical step in assuring SoC designers of the robustness of our CXL implementation”.

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“CXL will be a foundational interconnect technology in the data centers and networks of the future,” said Dr. Debendra Das Sharma, Intel Fellow and Director of I/O Technology and Standards Group, Data Center Group. “The availability of third party silicon IP like the PLDA XpressLINK CXL Controller IP lowers integration risks and helps ensure quicker proliferation of the CXL protocol across the industry ecosystem.”

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