Cadence Introduces Palladium Z2: Advancing SoC Verification With 4-State Emulation

4-State Emulation App accelerates simulations requiring X-propagation

Cadence Design Systems, Inc. announced a new portfolio of applications that significantly enhance the capabilities of its flagship Palladium Z2 Enterprise Emulation System. These domain-specific apps allow customers to manage increasing system design complexity, improving system-level accuracy and accelerating low-power verification for advanced applications, such as artificial intelligence and machine learning (AI/ML), hyperscale and mobile.

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designs are pushing the envelope on complexity, and customers need capacity, performance and debug efficiency to meet time-to-market demands. The new Cadence^® apps and updates individually offer industry-leading performance and features to address these growing challenges. The new and enhanced Palladium Apps are:

• 4-State Emulation App: Industry’s first 4-state emulation capability enables acceleration of simulations requiring X-propagation such as for low-power verification of complex SoCs with multiple switched power domains.
• Real Number Modeling App: Industry’s first real number model emulation capability enables acceleration of simulations on mixed-signal designs.​
• Dynamic Power Analysis App: A next-generation massively parallel architecture for multi-billion-gate, million-clock-cycle power analysis of complex SoCs that is up to 5X faster than its previous versions.​

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“To keep up with today’s advanced SoC design requirements, customers need an emulation solution that offers high performance with fast, predictable compile and debug,” said Dhiraj Goswami, corporate vice president, Hardware System Verification R&D at Cadence. “With the release of these new Palladium Apps, for the first time in our industry, our customers can now accelerate X-propagation and mixed-signal on emulation.”

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The Palladium Z2 emulation system is part of the broader Cadence Verification Suite and supports the company’s Intelligent System Design^™ strategy, enabling SoC design excellence.

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