GBT’s Automatic Correction of Integrated Circuits Connectivity Mismatches Non-Provisional Patent Application has been Approved for Prioritized Examination

GBT Technologies has been granted a fast track request by the United Stated Patent and Trademark Office for its nonprovisional patent application pertaining to the automatic correction of Integrated Circuits (IC) electrical connectivity mismatches. The patent application will undergo prioritized examination to accelerate the process. The original patent was filed on August 3, 2022 (application #17880055) to protect programmatic methodologies and algorithms to automate integrated circuits electrical connectivity mismatches correction, with the goal of shortening microchip’s design cycle, particularly for advanced nanometer nodes of 5nm and below.

Latest Aithority Insights : NVIDIA Raises the Standard of Low Code DevOps with the NVIDIA AI Enterprise 2.1

Layout Versus Schematic (LVS) checking process compares the IC’s mask with the schematic netlist to determine if they match. The comparison results are considered ‘pass’ (or ‘clean’) if all the electronic devices and connectivity that are described in the schematic match the devices and connectivity in the layout. A ‘fail’ (or ‘dirty’) results means connectivity and/or devices mismatches. Particularly with Analog or MIXED layout types, these mismatches would have to be fixed manually which is a tedious, time consuming, manual design work. A layout designer would have to debug the results, identifying the wrong electrical connections and/or device mismatches, and make the necessary layout modifications to achieve a ‘clean’ comparison.

GBT’s non-provisional patent application seeks to protect an algorithmic system and method to perform this process automatically. With a click of a button, the system is designed to read the IC’s schematic and layout data, compare the devices and electrical connectivity (wiring) and in case of mismatches detection, disconnect the faulty wires, and re-connect them in the layout to achieve a ‘clean’ LVS. The system is designed to automatically correct the layout, without causing any other LVS, geometrical (DRC), Reliability Verification (RV), and DFM (Design for Manufacturing) violations.

“We requested to expedite our LVS Automatic Correction nonprovisional patent (internal code name: ‘Sigma’) as we believe that it may have the capability to potentially impact the IC design world. GBT predicts a global growth in the semiconductor arena in the next decade and plans to invest vast efforts in this domain. Especially for advanced nodes, we believe there will be a need for productivity enhancement EDA technology to catch up with physics that dictates IC’s manufacturing processes. Small nodes, like 5nm and 3nm and below, are expected to create a whole world of challenges and an intelligent, efficient solutions are needed. We are working on programmatical approach to provide design automation solutions, identifying weak spots and bottlenecks within the IC layout design arena, and providing algorithmic methodologies to overcome challenges. One of the major verification processes within IC design cycle is LVS; Layout-vs-Schematic. In this process the physical IC layout is compared to its correspondence electrical schematic.

AI and ML News: Why SMBs Shouldn’t Be Afraid of Artificial Intelligence (AI)

This comparison process may result in connection mismatches between the schematic diagram and the mask layout data, particularly with Analog, RF, and MIXED layout types. A mismatch typically means a faulty electrical connection in the mask layout database that does not match its corresponding wiring in the schematic diagram. This may cause a circuit malfunction or wrong functional outcome. A correction of electrical connectivity mismatches within IC data can be a significant time-consuming process, especially with advanced nanometer chips, like 5nm and below, that may include billions of transistors. The technology underlying our non-provisional patent application presents an automated LVS correction system to analyze the data of an entire chip, checks for electrical connectivity mismatches and Auto-Correcting them with a click of a button. It’s a major challenge to perform such an operation programmatically and we are using advanced mathematics and AI technology to address the vast amount of data processing, complex mathematical analysis, concluding possible solutions, and executing auto-corrections. We consider this IP as one of GBT’s innovative IC design productivity enhancement technology, and plan to pursuit further R&D efforts in it in the future” stated Danny Rittman, the Company’s CTO.

There is no guarantee that the Company will be successful in researching, developing or implementing this system. In order to successfully implement this concept, the Company will need to raise adequate capital to support its research and, if successfully researched, developed and granted regulatory approval, the Company would need to enter into a strategic relationship with a third party that has experience in manufacturing, selling and distributing this product. There is no guarantee that the Company will be successful in any or all of these critical steps.

Future of AI-driven Customer Relationship:  Microsoft’s Viva Sales and the Future of AI-driven Customer Relationship and Experience Management

[To share your insights with us, please write to sghosh@martechseries.com]