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Rapid Silicon’s Raptor Software Out-Performs All EDA Tools in the Industry

Rapid Silicon, a provider of AI and intelligent edge focused FPGAs based on open-source technology,announced its commercial open-source FPGA EDA suite, Raptor, was awarded 24 verified unique wins and two ties, 2x more wins than the leading competitor, in the latest École polytechnique fédérale de Lausanne (EPFL) Combinatorial Benchmark Suite. This strong showing in the EPFL competition is attributed in large part to Rapid Silicon’s patent-pending “ABC-DE” algorithm.

While many commercial synthesis tools enter the EPFL benchmarking competition, Rapid Silicon is the only FPGA vendor to participate, breaking the traditional tight control FPGA companies have held over their EDA tools. Rapid Silicon’s Raptor software leads the programmable revolution as the industry’s first and only commercial open-source FPGA design suite.

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“These benchmarks are very important to the EDA community,” said Tony McDowell, director of open-source at Rapid Silicon. “Participation is growing, but the fact that Rapid Silicon is the only FPGA vendor to participate underscores our commitment to revolutionizing the FPGA industry. Even though our Raptor design software is already open-source by design, including it in open benchmarking is yet another way to accelerate innovation and foster the building of a robust ecosystem for hardware developers.”

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The EPFL Combinational Benchmark Suite is an open competition to test the efficiency of synthesis, in both implementation size and performance. To maintain fairness, the EPFL publishes a suite of unoptimized digital designs used to compare tools, and the results are submitted to the EPFL team and verified.

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EPFL, located in Switzerland, is one of Europe’s most prestigious science and technology universities. The EPFL Combinatorial Benchmark Suite, which was first introduced in 2015, is used to define new comparative standards for the logic optimization and synthesis community. The latest open-source benchmark suite includes approximately 20 combinational designs comprised of 10 arithmetic computational algorithms and 10 random and control designs, which are intentionally not optimized in order to test the ability of synthesis and optimization design tools. These sub-optimal designs are then synthesized to a LUT-6 architecture. The EPFL results are verified by an independent committee then published as confirmed winners. The latest competition results can be found on the EPFL site.

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