Enabling AI Chip Design from the Data Center to the Edge
Synopsys, Inc. (Nasdaq : SNPS ) today announced that Yankin Tanurhan, vice president of engineering for Processors, Security, NVM, and SoC Design in Synopsys’ Solutions Group, will chair the 2018 AI Hardware Summit, and Dr. Thomas Andersen, head of AI and Machine Learning in the Design Group, will present “Device Intelligence: AI Chip Design from the Data Center to the Edge” at the conference on Tuesday, September 18, at 1:30 p.m. at the Computer History Museum in Mountain View, Calif. In addition, Synopsys will demonstrate its DesignWare® EV6x Embedded Vision Processor IP in the sponsor exhibit area.
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Forecasts predict that the AI (chipsets) market is expected to grow from USD 7.06 billion in 2018 to USD 59.26 billion by 2025, at a CAGR of 35.5% from 2018 to 2025 (Business Wire, 2018). As a partner to the world’s most innovative companies, Synopsys has worked alongside AI pioneers to establish an early lead in identifying AI hardware design needs, making the necessary investments to address those requirements—from reference flows, to new tool features, to the industry’s most comprehensive AI-ready DesignWare IP portfolio. Today, almost all AI accelerators in data centers worldwide were designed and verified with Synopsys solutions.
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As the first and only conference dedicated solely to the ecosystem developing hardware accelerators for neural networks and computer vision, the AI Hardware Summit provides a key opportunity for technology leaders from AI chip start-ups, semiconductor companies, system vendors/OEMs, data centers, and end users to share experiences and build a comprehensive understanding of the architectural roadmap of the emerging AI chip market.
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