Achronix Announces Immediate Availability of Speedcore GEN4 eFPGA IP for AI/ML and Networking Hardware Acceleration Applications
New Machine Learning Processor Blocks Deliver 300% Higher Performance for AI/ML Applications
Achronix Semiconductor Corporation, a leader in FPGA-based hardware accelerator devices and high-performance eFPGA IP, announced immediate availability of its Speedcore™ Gen4 embedded FPGA (eFPGA) IP for integration into users’ SoCs. Speedcore Gen4 increases performance 60%, reduces power by 50% and die area by 65% while retaining the original Speedcore eFPGA IP’s abilities to bring programmable hardware-acceleration capabilities to a broad range of compute, networking and storage systems for interface protocol bridging/switching, algorithmic acceleration and packet processing applications.
With the Speedcore Gen4 architecture, Achronix adds the new Machine Learning Processor (MLP) to the library of available blocks and delivers 300% higher system performance for artificial intelligence and machine learning (AI/ML) applications. MLP blocks are highly flexible, compute engines tightly coupled with embedded memories to give the highest performance per watt and lowest cost solution for AI/ML applications.
“Achronix Speedcore eFPGA with Gen4 architecture provides an optimal balance of hardware acceleration previously found only in ASIC implementations,” said Robert Blake, president and CEO of Achronix Semiconductor. “Our new architecture adds the flexibility and reprogrammability of our proven FPGA technology to support exploding demand for new AI/ML and high data bandwidth applications.”
The dramatic increase in fixed and wireless network bandwidth, coupled with the redistribution of processing, and the emergence of billions of IoT devices will stress traditional network and compute infrastructure. Classic Cloud and Enterprise Data Center computing resources and communications infrastructure can no longer keep pace with exponential growth in data rates, the rapidly changing security protocols, or the many new networking and connectivity requirements. Traditional multicore CPUs and SoCs cannot meet these requirements unaided. They need hardware accelerators, often reprogrammable to pre-process and offload computations to increase the systems’ overall compute performance.